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74AC175 * 74ACT175 Quad D-Type Flip-Flop
November 1988 Revised November 1999
74AC175 * 74ACT175 Quad D-Type Flip-Flop
General Description
The AC/ACT175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D-type inputs is stored during the LOW-to-HIGH clock transition. Both true and complemented outputs of each flipflop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D-type inputs, when LOW.
Features
s ICC reduced by 50% s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s Asynchronous common reset s True and complement output s Outputs source/sink 24 mA s ACT175 has TTL-compatible inputs
Ordering Code:
Order Number 74AC175SC 74AC175SJ 74AC175MTC 74AC175PC 74ACT175SC 74ACT175SJ 74ACT175MTC 74ACT175PC Package Number M16A M16D MTC16 N16E M16A M16D MTC16 N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Body 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names D0-D3 CP MR Q0-Q3 Q0-Q3 Description Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009936
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74AC175 * 74ACT175
Functional Description
The AC/ACT175 consists of four edge-triggered D-type flipflops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the LOWto-HIGH clock (CP) transition, causing individual Q and Q outputs to follow. A LOW input on the Master Reset (MR) will force all Q outputs LOW and Q outputs HIGH independent of Clock or Data inputs. The AC/ACT175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
Truth Table
Inputs @ tn, MR = H Dn L H
H = HIGH Voltage Level L = LOW Voltage Level tn = Bit Time before Clock Pulse tn+1 = Bit Time after Clock Pulse
Outputs @ tn+1 Qn L H Qn H L
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC175 * 74ACT175
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum Input Leakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 4.0 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 75 -75 40.0 A mA mA A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH = -12 mA IOH = -24 mA IOH = -24 mA (Note 2) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC175 * 74ACT175
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 4.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 40.0 A mA mA mA A V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 5) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol fMAX tPLH Maximum Clock Frequency Propagation Delay CP to Qn or Qn tPHL Propagation Delay CP to Qn or Qn tPLH Propagation Delay MR to Qn tPHL Propagation Delay MR to Qn
Note 7: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 149 187 2.0 1.5 2.5 1.5 3.0 2.0 3.0 2.0 Typ 214 244 9.5 7.0 8.5 6.0 7.5 5.5 8.5 6.0 12.0 9.0 13.0 9.5 12.5 9.0 11.0 8.5 Max
TA = -40C to +85C CL = 50 pF Min 139 187 2.0 1.0 2.0 1.5 2.5 1.5 2.5 1.5 13.5 9.5 14.5 10.5 13.5 10.0 12.5 9.0 ns ns ns ns Max MHz Units
Parameter
(V) (Note 7) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
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74AC175 * 74ACT175
AC Operating Requirements for AC
VCC Symbol tS tH tW tW Parameter Setup Time, HIGH or LOW Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW Recovery Time MR to CP
Note 8: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 2.0 1.0 1.0 1.0 2.5 2.0 2.5 2.0 -2.0 -1.0 4.5 3.0 1.0 1.0 4.5 3.5 4.5 3.5 0 0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 4.5 3.0 1.0 1.0 4.5 3.5 5.0 ns 3.5 0 0 ns ns ns ns Units
(V) (Note 8) 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
tREC
3.3 5.0
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 9) fMAX tPLH tPHL tPLH Maximum Clock Frequency Propagation Delay CP to Qn or Qn Propagation Delay CP to Qn or Qn Propagation Delay 5.0 MR to Qn tPHL Propagation Delay 5.0 MR to Qn
Note 9: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 175 2.0 2.0 Typ 236 6.0 7.0 10.0 11.0 Max
TA = -40C to +85C CL = 50 pF Min 145 1.5 1.5 11.0 12.0 Max MHz ns ns Units
5.0 5.0 5.0
2.0
6.0
9.5
1.5
10.5
ns
2.0
5.5
9.5
1.5
10.5
ns
AC Operating Requirements for ACT
VCC Symbol tS (H) tS (L) tH tW tW trec Setup Time Dn to CP Hold Time, HIGH or LOW Dn to CP CP Pulse Width HIGH or LOW MR Pulse Width, LOW Recovery Time, MR to CP 5.0 5.0 5.0 5.0 Parameter (V) (Note 10) 5.0 TA = +25C CL = 50 pF Typ 3.0 3.0 0 4.0 4.0 0 2.0 2.5 1.0 3.0 3.0 0 TA = -40C to +85C CL = 50 pF Guaranteed Minimum 2.0 2.5 1.0 3.5 4.0 0 ns ns ns ns ns Units
Note 10: Voltage Range 5.0 is 5.0V 0.5V
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 45.0 Units pF pF V CC = OPEN V CC = 5.0V Conditions
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74AC175 * 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body Package Number M16A
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74AC175 * 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
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74AC175 * 74ACT175
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
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74AC175 * 74ACT175 Quad D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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